Ex parte WRISTERS et al. - Page 2




          Appeal No. 1999-1517                                                        
          Application No. 08/837,523                                                  


               The disclosed invention is directed to providing an                    
          appropriate doping level of ions by forming a source, a drain               
          and a gate using a single diffusion step.  The technique                    
          provides for the normal doping of the source/drain region.                  
          After the formation of the gate structure, side spacers are                 
          formed beside the gate structure.  After a layer of silicon                 
          dioxide is applied to the surface of the gate structure and                 
          the substrate, a polysilicon layer with doping ions embedded                
          therein is applied to the surface of the silicon oxide layer.               
          A heat treatment causes the doping ions embedded in the                     
          polysilicon layer to diffuse through the silicon layer into                 
          the substrate where the source/drain regions are formed, and                
          to diffuse into the gate structure, whereby the upper portion               
          of the gate structure becomes conducting and the gate                       
          electrode is formed by the same heat treatment.  A further                  
          understanding of the invention can be obtained by the reading               
          of the following claim.                                                     
               11.  A method of making an IGFET, comprising the                       
               steps of:                                                              
               providing a device region of a first conductivity                      
                    type in a semiconductor substrate;                                
               forming a gate insulator on the device region;                         
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