Appeal No. 2001-2351
Application No. 08/772,443
appellants that Parks does not teach that the current data
transfer is simultaneously received by the data buffer and the
host system. At page 8 of the answer, the examiner argues to the
effect that the claimed feature is met by Parks because the data
received from the peripheral devices is sent to local memory 324
in Figure 3 and FIFO 504 in Figure 5 at the same time.
Although the examiner is correct in his characterization of
Parks’ teaching, this teaching does not meet the claimed subject
matter. The claims require that the data transfer is
simultaneously received by the data buffer and the host system.
In Parks, the data transfer is simultaneously received at local
memory 324 and the FIFO 504 of the snooping bus bridge 320. See
column 7, lines 48-51. Even if it is assumed that the data
buffer of the claims is met by Parks’ local memory 324, the FIFO
504 is not a part of the host system. The host system of Parks
comprises processor 302 and the data in FIFO 504 is subsequently
transferred to the processor.
The Rejection under 35 U.S.C. § 102(e)
Claims 3, 11, 12, 18, 21, 22 and 32-34
Whereas we will not sustain the rejection of any independent
claim, we will not sustain the rejection of dependent claims 3,
11, 12, 18, 21, 22 and 32-34 as anticipated by Parks.
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