Appeal No. 1999-1098
Application 08/627,313
Specifically, the memory blocks (figure 1, B1-B64) are
arranged on a semiconductor substrate (10) to surround
peripheral circuits (11-14) which are situated at the center
of each unit block (U1-U4). Each memory block includes a
plurality of word lines (figure 2, item 17), a plurality of
bit lines (figure 2, item 18, 19) crossing the word lines, and
a plurality of memory cells (figure 2, item 20) each
corresponding to a crossing point of the word line and the bit
line.
Multiple embodiments are disclosed (figures 6-13).
Appellants' independent claims 1 and 13, reproduced
below, are representative of the invention:
1. A semiconductor memory device, comprising:
a semiconductor substrate;
a plurality of memory blocks, each memory block having an
outer peripheral boundary delineating an entire area of the
memory block with each memory block including a plurality of
word lines, a plurality of bits lines crossing said plurality
of word lines, and a plurality of memory cells corresponding
to crossing points of said plurality of word lines and said
plurality of bit lines positioned within the entire area of
the memory block, a portion of the outer peripheral boundary
of said each memory block corresponding to a portion of the
outer peripheral boundary of each adjacent memory block, said
plurality of memory blocks being arranged on said
semiconductor substrate to completely surround a center of
said semiconductor substrate; and
2
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