Appeal No. 1999-1098
Application 08/627,313
necessarily weigh all of the evidence and argument.").
Accordingly, we now consider the claims on appeal.
Appellants first point out that their admitted prior art3
describes the disadvantages associated with the prior art and
Appellants' claims clearly distinguish over this prior art.
Next, Appellants summarize that the Kusunoki reference4
describes the use of memory mats and mat periphery circuits
which correspond to the memory blocks and the peripheral
circuit recited in claim 1. However, Appellants assert that
the periphery circuits of Kusunoki are not located at the
center of the memory mats as required by claim 1.
As regards Seefeldt, Appellants argue that it is clear 5
legal error for the Examiner not to address the differences
between the claimed semiconductor memory device having a
plurality of memory blocks and a peripheral circuit, and the
gate array arrangement of Seefeldt. Appellants further argue
that since none of the applied prior art references suggests
3Brief, page 9
4Brief, pages 9-10
5Brief, page 11
7
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