Ex parte SAKASHITA et al. - Page 3




          Appeal No. 1999-1098                                                        
          Application 08/627,313                                                      


               a peripheral circuit for said plurality of memory blocks               
          arranged on said semiconductor substrate at a center of said                
          memory blocks, completely surrounded by said plurality of                   
          memory blocks.                                                              


          13. A semiconductor memory device comprising:                               
               a semiconductor substrate;                                             
               first through fourth memory blocks arranged on said                    
          semiconductor substrate to surround a center of said                        
          semiconductor substrate, each memory block having a                         
          rectangular shape and including a plurality of word lines, a                
          plurality of bit lines crossing said plurality of word lines,               
          and a plurality of memory cells corresponding to crossing                   
          points of said plurality of word lines and said plurality of                
          bit lines; and                                                              
               a peripheral circuit for said first through fourth memory              
          blocks, disposed on said semiconductor substrate at a center                
          of said first through fourth memory blocks; wherein                         
               said first memory block is arranged so that one shorter                
          side of said first memory block is adjacent to one longer side              
          of said fourth memory block and one longer side of said first               
          memory block is located on an extension of one shorter side of              
          said fourth memory block,                                                   
               said second memory block is arranged so that one shorter               
          side of said second memory block is adjacent to another longer              
          side of said first memory block and one longer side of said                 
          second memory block is located on an extension of another                   
          shorter side of said first memory block,                                    
               said third memory block is arranged so that one shorter                
          side of said third memory block is adjacent to another longer               
          side of said second memory block and one longer side of said                
          third memory block is located on an extension of another                    
          shorter side of said second memory block, and                               
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