Appeal No. 2001-2692 Page 14
Application No. 08/789,001
Turning to the reference, Aubertine discloses "a method for physical layout of
elements of a computer system by assigning I/O pins for physical package design. . . ."
Col. 6, ll. 24-25. For our part, we find that the method assembles a circuit design in
accordance with parameters provided by a user. Specifically, "the first step 1 of our
method is an input from a user of the assignment method which defines or establishes
net priorities." Id. at ll. 58-60. Also, "[s]tep 1 of the method begins with accepting as
input the placement of all components at each system level and the logical association
of all nets in accordance with top-down design." Col. 7, ll. 28-31.
We further find that the assembly is also performed in accordance with several
predefined circuit design rules. For example, "[a] test is made to determine if the
results of Step 3 are legal with respect to the lowest level component of the system.
(Design information describing the placement of components with respect to
other components across the system is used to make this determination.)" Id. at 7-11.
The reference's design information is a rule.
Furthermore, [i]n selecting the component I/Os at the different levels of the
system for assignment to nets, design constraints that are established for these nets
must be obeyed." Col. 4, ll. 11-13. These design constraints are rules. One such rule
is that "the wire length must be kept to a minimum." Id. at l. 21. Therefore, we affirm
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