Appeal No. 2001-2692 Page 9
Application No. 08/789,001
Here, Modarres explains that "[t]he preferred embodiment of [its] invention
involves an automated system . . . which, given the total area of a chip, a hierarchy of
functions, and a net list of the interconnections among terminal functions, places such
functions within the chip so as to minimize the required area occupied by such functions
and their interconnections, and to maximize the probability that such interconnections
can be routed within that area." Col. 6, ll. 31-39. For our part, we find that the system
assembles a circuit design in accordance with parameters provided by a user.
Specifically, "the user specifies the 'root function' I-5 -- the function from which
automatic placement should begin -- and the number of levels I-6 below the root
function which the system should automatically place." Col. 8, ll. 46-50.
We further find that the assembly is also performed in accordance with several
predefined circuit design rules. For example, "[a]s a default [rule], [the system] will
place the clock in the center of the chip (in a vertical orientation), and will begin
automatic placement at the top (chip) function and place functions throughout all levels
of the hierarchy." Col. 9, ll. 34-38. Another example of a rule is that "[t]he system
traverses the hierarchy in a 'preorder' (parent before children, as opposed to 'postorder,'
children before parent) fashion. . . ." Id. at ll. 50-53. Furthermore, "[t]he system
employs two methods to partition the children into two groups," col. 14, ll. 15-16. A
predefined rule is used to select between the two methods. Specifically, "[t]he first
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