Appeal No. 2001-2692 Page 2
Application No. 08/789,001
The appellants complain, however, that "[i]nterconnecting input, output, and bi-
directional buffers can be time consuming and tedious, particularly if boundary scan or
other test structures are included in the circuit design." (Id. at 2.) For board testing, a
boundary scan path that includes each I/0 buffer of an IC is provided. The path allows
each I/0 pad of the IC to be controlled and observed. (Id.)
Accordingly, the appellants' invention provides a user interface for receiving
parameters from a circuit designer. Assembly rules, which define available I/0 cells,1
available boundary scan logic modules, and appropriate interconnections for various
combinations thereof, are also provided. (Id. at 5.) A computer program selects and
interconnects the I/0 cells and the boundary scan logic modules to form interface
modules. More specifically, the I/0 cells and the boundary scan blocks are selected
according to the parameters and are interconnected according to the rules. (Id. at 4-5.)
A further understanding of the invention can be achieved by reading the following
claim.
1. A data processing system for automatically selecting and
interconnecting a number of macro cells selected from a component
library to form a first circuit design wherein each one of the number of
1The cells are input, output, or bi-directional buffers. (Spec. at 5.)
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