Ex Parte Lattimore et al - Page 1




              The opinion in support of the decision being entered                  
              today was not written for publication in a law journal                
              and is not binding precedent of the Board.                            
                                                             Paper No. 13           


                     UNITED STATES PATENT AND TRADEMARK OFFICE                      
                                                                                   
                         BEFORE THE BOARD OF PATENT APPEALS                         
                                 AND INTERFERENCES                                  
                                                                                   
            Ex parte GEORGE MCNEIL LATTIMORE, DONALD GEORGE MIKAN JR.,              
                         JOSE ANGEL PAREDES and GUS WAI-YAN YEUNG                   
                                                                                   
                                Appeal No. 2002-0140                                
                             Application No. 09/435,864                             
                                                                                   
                                      ON BRIEF                                      
                                                                                   

         Before KRASS, RUGGIERO and DIXON, Administrative Patent Judges.            
         KRASS, Administrative Patent Judge.                                        


                                 DECISION ON APPEAL                                 
              This is a decision on appeal from the final rejection of              
         claims 1-4, 6, 7, 9, 14, 15 and 17.  Claims 5, 8, 10-13, 16 and            
         18 stand allowed by the examiner.                                          
              The invention is directed to multi-staged circuits which use          
         multi-clocks for timing between stages.  These circuits have an            
         undeterminable clock underlap problem brought about by                     

                                        -1–                                         





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