Appeal No. 2002-0140
Application No. 09/435,864
the clock signals phase 3 and phase 34, it is clear that the
output of the first stage is controlled using the first and
second clock signals, as claimed.
With regard to instant claim 2, it is also clear that the
second clock signal, phase 3, is also received in a second stage,
logic gates 12 and 13, and the output of the second stage, Vout,
is controlled using this second clock signal.
It appears to us that the examiner has indeed established a
prima facie case of anticipation with regard to the subject
matter of instant claims 1 and 2.
For their part, appellants contend that Wu does not teach
the features of controlling the outputs of the first and second
stages using the second clock signal. For the reasons supra, we
disagree. If the clock signal has an effect on the output, it
may be said to “control” the output.
Appellants also contend that the output of Wu’s circuit is
not controlled by an output from a first stage using a first
clock signal, but instead, is controlled by the skew effect of
the transistors. Appellants further explain that the circuits of
Wu “use the same clocks...but change both the way the transistors
are connected throughout the circuit as well as reducing the
-4–
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