Appeal No. 2002-0140
Application No. 09/435,864
head of line 16) being triggered in response to a rising edge of
the first clock signal phase 34, as required by instant claim 3.
Moreover, the figure also shows a falling edge of output V3 being
triggered by a rising edge of second clock signal phase 3. With
regard to stabilizing the output, as recited in claim 6, that
appears to be the purpose of Wu in solving the clock-skew race
problem.
Accordingly, we will sustain the rejection of claims 3, 4
and 6 under 35 U.S.C. § 102(b).
We now turn to the rejection of claims 9, 14, 15 and 17
under 35 U.S.C. § 102(b) as anticipated by Levy.
The examiner applies Figure 5 of Levy to independent claim 9
as follows:
The claimed first stage comprises a logic device 516 with at
least one output, at line 517. A first transistor Q3 is
connected to a first clock source 530 at a first transistor gate
wherein the first transistor drain is connected to an output port
of the logic device. A second transistor 512 is connected to a
second clock source 528 at a second transistor gate, wherein the
second transistor drain is connected to the first transistor at a
first transistor source. A second stage 522 is connected to the
first stage for receiving the first stage output from inverter
-7–
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