Appeal No. 2003-0886
Application No. 09/466,845 Page 8
Chen, we find that although Chen is directed to an MROM including
wordlines and bitlines, Chen does not disclose the use of a
silicide layer formed on and in contact with the surface of the
second conductivity type high concentration impurity diffusion
layer (bitlines).
Turning to Hirano, we find that Hirano is directed to a
technique for forming a thin film transistor (TFT) which is
widely used in an active matrix type of liquid crystal device
(LCD) (col. 1, lines 13-16). The TFT has a stable silicide layer
formed apart from a channel region (col. 1, lines 9 and 10). As
shown in prior art figure 1F, relied upon by the examiner,
silicide layer 108 directly contacts the channel region of I-
layer 104 (col. 2, lines 54-56). As a result, over etching of
the lower layer 104 cannot be avoided (col. 2, lines 64 and 65).
An object of the invention is to provide a TFT with a short
channel length, so that direct contact between the I-layer 104
and the silicide layer is prevented (col. 4, lines 38 and 39).
Hirano discloses (col. 5, lines 13-17) "forming source and drain
electrodes, each of said source and drain electrodes comprising a
metal silicide layer formed in a surface portion of the
semiconductor film and a metal portion apart from the first mask
section." As shown in figure 3C, a Cr silicide layer 8 is formed
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