Appeal No. 1999-0288
Application No. 08/538,071 Page 15
based upon the specific address associated with a specific
process identified by a bit in a machine state register, as
recited in claim 6. In addition, because each of the up to 500
Processor-Memory Elements contains a Performance Monitoring Chip,
which includes a status register, we find no suggestion that the
status register in Brantley is a machine state register.
Moreover, with respect to the examiner's assertion (final
rejection, pages 4 and 5) that it would have been obvious to
place the process recognition bit in a machine state register
because it would ensure that the specific process, along with the
events associated with the process, are identified correctly, in
order to enable the counters correctly for performance monitoring
of those events and processes, we find no recognition of any
problem in Wibecan or Brantley with respect to incorrect
identification of events within a process, that would suggest
placing a process recognition bit within a machine state
register.
As stated, supra, with respect to appellants' assertion that
Wibecan, Brantley, and Gover do not show the use of MMCRs or
machine status registers to perform performance monitoring based
upon an effective address in a specific process, the examiner
takes the position (answer, page 6) that appellants' claims seem
Page: Previous 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Next
Last modified: November 3, 2007