Appeal No. 2004-0721
Application No. 09/401,409
dielectric material directly on a pad and lines of a
topographical substrate, depositing an oxide on the low-k
dielectric material and planarizing the oxide using a CMP
process. Further details of this appealed subject matter are set
forth in representative independent claim 1 which reads as
follows:
1. A process for making a multi-layer interconnect,
comprising:
depositing directly on a pad and lines of a topographical
substrate a low-k dielectric material having a height greater on
said pad than on said lines, wherein said low-k dielectric
material has a dielectric constant of less than 2.8;
depositing an oxide on said low-k dielectric material;
planarizing said oxide using a CMP process;
making via holes through said oxide and said low-k
dielectric material, wherein prior to making via holes, all of
said deposited low-k dielectric material remains as deposited on
said pad and lines to form said multi-layer interconnect.
The reference set forth below is relied upon by the examiner
in the section 102 rejection before us:
Xu et al. (Xu) 6,207,554 Mar. 27, 2001
(filed Jul. 12, 1999)
All of the appealed claims stand rejected under 35 U.S.C.
§ 102(e) as being anticipated by Xu.1
1 As indicated on page 4 of the brief, the claims on appeal
will stand or fall together. Accordingly, in assessing the
(continued...)
2
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