Appeal No. 2006-2525
Application No. 10/178,672
Claims 8 and 9 stand rejected under 35 U.S.C. § 103 as being unpatentable over
Celler, Leipold, and Wong.
We refer to the Rejection (mailed May 5, 2005) and the Examiner’s Answer
(mailed Mar. 20, 2006) for a statement of the examiner’s position and to the Brief (filed
Jan. 6, 2006) and the Reply Brief (filed May 18, 2006) for appellants’ position with
respect to the claims which stand rejected.
OPINION
Based on appellants’ arguments in the Brief, we will decide the appeal on the
basis of rejected claim 3.1 See 37 CFR § 41.37(c)(1)(vii).
The examiner finds that Celler teaches the subject matter of instant claim 3
except for a patterned low resistivity buried layer and the active RF device as it relates
to the patterned low resistivity buried layer. Celler teaches a digital CMOS device (col.
4, ll. 4-6). Although not express in the statement of the rejection (Answer at 3-4), Celler
also does not teach how the digital circuit might relate to a patterned low resistivity
buried layer. The examiner further finds that Leipold teaches forming a patterned low
resistivity buried layer, as specified by the claim, only beneath a digital CMOS circuit
(e.g., under field effect transistors 12; Leipold Fig. 1). The examiner concludes that the
1 Appellants’ remarks in response to the rejection of claims 8 and 9 rely on the argued deficiencies
in the rejection applied against base claim 3.
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