Appeal 2006-0016
Application 10/347,536
Here, claims 37 and 60 recite in pertinent part the following
limitations: "blocking transactions that collide with said Read transaction
from being received by said processor during processing of said Read
transaction. . . ." Considering these limitations, the independent claims
require blocking colliding transactions from being received by a processor
that requested a Read transaction.
B. ANTICIPATION DETERMINATION
"Having construed the claim limitations at issue, we now compare the
claims to the prior art to determine if the prior art anticipates those claims."
In re Cruciferous Sprout Litig., 301 F.3d 1343, 1349, 64 USPQ2d 1202,
1206 (Fed. Cir. 2002). "[A]n invention is anticipated if the same device,
including all the claim limitations, is shown in a single prior art reference.
Every element of the claimed invention must be literally present, arranged as
in the claim." Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236,
9 USPQ2d 1913, 1920 (Fed.Cir. 1989) (citing Perkin-Elmer Corp. v.
Computervision Corp., 732 F.2d 888, 894, 221 USPQ 669, 673 (Fed. Cir.
1984); Kalman v. Kimberly-Clark Corp., 713 F.2d 760, 771-72, 218 USPQ
781, 789 (Fed. Cir. 1983)). "[A]bsence from the reference of any claimed
element negates anticipation." Kloster Speedsteel AB v. Crucible, Inc., 793
F.2d 1565, 1571, 230 USPQ 81, 84 (Fed. Cir. 1986).
Here, Donaldson describes "[a] cache coherency protocol for a multi-
processor system which provides for read/write, read-only and transitional
data states and for an indication of these states to be stored in a memory
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