Appeal 2006-2671
Application 09/508,572
over insulating layer 12, even though, as Appellants point out, the precise
dimensions of the thicknesses of the portions of the layer are not disclosed
by Merchant.
We find one of ordinary skill in this art would have found from
Merchant’s Fig. 4, which shows protective metal layer 22 deposited on
conductive metal layer 20 (id., col. 4, l. 66, to col. 5, l. 1), that protective
layer 22 covers all of conductive metal layer 20 including the depression in
layer 20 extending into opening 14. Protective layer 22 can be selected from
a number of metals and metal alloys (id., col. 5, ll. 14-63). In Merchant’s
Fig. 5, conductive metal layer 20, with protective metal layer 22 thereon, is
subjected to reflow “such that [conductive metal layer 20] uniformly fills the
opening 14” (id., col. 5, l. 64, to col. 6, l. 23).
We find MacNaughton would have disclosed to one of ordinary skill
in this art semiconductor integrated circuit devices having an aluminum
conductive interconnect layer in a vias (MacNaughton, e.g., col. 1,
ll. 16-30). Merchant acknowledges it was known that the thickness of the
conductive layers in via openings is uneven, resulting in “thinner regions”
(id., col. 1, ll. 45-53). MacNaughton addresses this problem by forming a
continuous aluminum conductive layer at a low temperature and depositing a
second aluminum layer thereon at a higher temperature to form the
conductive layer of the device (id., col. 2, ll. 39-48). In MacNaughton’s
method, opening 14 is formed in insulating layer 12 on substrate 10, all of
which is covered with barrier layer 16 as illustrated in Fig. 1 (id., col. 3,
ll. 8-22).
11
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