Appeal 2007-2105
Application 10/762,445
lowering. Appellants contend that Hori not only increases the electric field
adjacent to the drain, which teaches away from reducing the DIBL problem,
but also fails to show a Vss connection region under the source region (Br.
8). The Examiner contends that the bit line or the Vss connection region in
Hori is “under the bottom of the recess (14) and under the source 7b”
(Answer 9). The Examiner further asserts that since the Vss region is fully
recessed in relation to the source region, it will reduce the DIBL (Answer
10).
The issue, therefore, is whether the Examiner erred in rejecting the
claims under 35 U.S.C. §§ 102(e) and 103(a). The issue specifically turns
on whether Hori anticipates Appellants’ claimed invention by disclosing a
Vss connection region situated under the bottom of the recess and under the
source of a floating gate memory cell.
FINDINGS OF FACT
The following findings of fact (FF) are relevant to the issue involved
in the appeal and are believed to be supported by a preponderance of the
evidence.
1. Hori relates to nonvolatile semiconductor memory devices
(Abstract) wherein a stacked floating gate is positioned over a stepped
channel region (col. 9, ll. 5-17).
2. As depicted in Figure 1A, source region 7 includes a high-
concentration impurity layer 7a and a low-concentration impurity layer 7b
(col. 9, ll. 64-66).
3. The low-concentration impurity layer 7b is provided between
the high-concentration impurity layer 7a and the channel region 9 and faces
4
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