Appeal 2007-2460
Application 10/709,179
STATEMENT OF THE CASE
Applicants’ (“ASE’s”) invention relates to a method of fabricating
bumps on the backside of a chip. (Specification, ¶ 3). ASE states that most
electronic products are designed to be as light and compact as possible. (Id.
at ¶ 6). To facilitate light and compact designs, multi-chip packages have
been developed, such as having a plurality of chips stacked on top of each
other and enclosed by a molding compound. (Id.). ASE’s specification
states that a method of fabricating bumps on the backside of a chip would
have the potential to reduce the size of a multichip package structure. (Id. at
¶ 15).
There is one independent claim on appeal, claim 15. ASE states that
claim 15 is representative of the claims on appeal for each of the rejections
on appeal. (Appeal Br. at 4). Claim 15 is directed to a method of
fabricating bumps on the backside of a chip. Specifically, claim 15 reads as
follows:
A method of fabricating bumps on a backside of a chip,
comprising the steps of:
providing the chip with an active surface having at least a
bonding pad thereon and the backside;
forming at least a bump pad on the backside of the chip;
and
forming a bump on the bump pad.
The Examiner made three (3) prior art rejections as follows:
i) Claims 15, 16 and 18 are rejected under 35 U.S.C. §
102(e) as anticipated by Ono, U.S. Published Application
2003/0107129 (“Ono”)
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