Appeal 2007-2460
Application 10/709,179
bump pad structure. Rohm & Haas Co. v. Brotech Corp., 127 F.3d
1089, 1092, 44 USPQ2d 1459, 1462 (Fed. Cir. 1997)(Nothing in the
rules or in jurisprudence requires trier of fact to credit unsupported or
conclusory assertions).
ASE contends that Ono does not teach forming a bump pad on
the “backside” of a chip. (Appeal Br. at 6). ASE states that the Ono’s
second interconnect 14 is located on an area other than where the
semiconductor chip 15 is located. (Id.). Ono Figure 2 however,
clearly depicts the second interconnect 14 as being located on the
backside of chip 15.
ASE argues that Ono Figure 2 is in error as the figure
contradicts Figures 3-4B, especially Figure 3. (Reply Br. at 7). In
particular, ASE states that none of the through holes 13 in Ono Figure
3 are aligned with or located right above the bumps 19, whereas
Figure 2 depicts the through holes above or to the located right above
of the bumps. (Id.).
Ono’s second interconnect 14 of Figure 2 has a portion that is
located beneath the chip 15 and a portion that extends beyond the
semiconductor chip. The Examiner found that the through holes of
Figure 3 represents an embodiment where the through holes are
located underneath the portion of the second interconnect that extends
beyond the chip. The Examiner’s finding is consistent with Ono’s
figures and Ono’s description of its figures. Furthermore, Ono states
that Figure 3 is “an example” of the first interconnect in a top plan
view and thus Ono’s invention is not limited to what is depicted in
Figure 3.
13
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