Appeal 2007-3623
Application 10/035,747
4. In the conventional circuit, a zero value result (+ or -) is
represented by an operand where (col. 1, ll. 56-64):
sign= ‘0’ or ‘1’ bit,
exponent=a sequence of eight ‘0’ bits,
magnitude=a sequence of twenty-three ‘0’ bits.
5. In the conventional circuit, when the arithmetic section 14
performs an operation that results in a value other than an ordinary operand
value, the arithmetic unit outputs a signal indicating that the result is zero,
infinity or not a number to the generator circuit 22. In response, the circuit
22 generates the appropriate output floating point number as per the IEEE
standard of special operands set. (Col. 2, ll. 55-59).
6. In the conventional circuit, interposed between the register file
and the arithmetic section 14 are detectors 24 and 26. One detector 24 or 26
is provided for each operand input path. The detectors 24 and 26 each
receive a respective operand x or y and determines whether or not the
received operand represents a special operand. If not, the detector 24 or 26
simply outputs the operand x or y to the arithmetic section 14. However, if
the detector 24 or 26 detects that the operand x or y represents a special
operand, the detector 24 or 26 identifies the type of the operand--the detector
determines which of the special operands the received operand x or y
represents. (Col. 3, ll. 11-21).
7. FIG. 2 shows an exemplary special operand generator circuit 22
in greater detail. As shown, the special operand generator circuit 22
includes first and second multiplexers 222 and 224.
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