Appeal 2007-3958
Application 10/611,229
(12), and a second conductive layer (14) formed on the insulation barrier
structure (13) (Kim, col. 9, ll. 46-68). Kim discloses the gate dielectric layer
(11) can be formed from silicon oxide layer (Kim, col. 9, ll. 3-4). The
Examiner found that Sato discloses the trenches (11) of an electrically
erasable nonvolatile semiconductor memory device have vertical sidewalls.
The side surfaces of the opposing projecting portions are parallel to each
other. The Examiner concluded that it would have been obvious to a person
having ordinary skill in the art at the time of invention to form the trench of
Kim having vertical sidewalls as taught by Sato with the reasonable
expectation that there would not have been any adverse effect on the
functionality of the device (Answer 3-4).
Appellant has not argued that there is no suggestion or motivation to
combine the teachings of Kim and Sato.3 Rather, Appellant’s principal
argument is that Kim and Sato, even if combined, do not teach the claimed
invention because Kim fails to teach “a first conductive film formed on the
first insulating film,” as recited in claim 1 (Br. 10-12). In other words,
Appellant asserts that the dielectric layer (11) of Kim is not an insulating
layer as required by claim 1.
We do not find Appellant’s arguments persuasive. Kim discloses the
first conductive layer (12) is formed on the gate dielectric layer (11). Kim
discloses that the layer (11) can be formed from a silicon oxide layer. This
is the same material (silicon oxide) that has been described by the Appellant
as suitable for forming a gate insulation film (Specification 14:12-14).
3 Appellant also has not argued that there is no suggestion or motivation to
combine the teachings of Gardner with Kim and Sato. Rather, Appellant
states “[t]he disclosure of Gardner is insufficient to cure the above-discussed
deficiencies of Kim and Sato” (Br. 17).
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