Appeal No. 94-0809
Application 07/707,365
were canceled by amendment filed July 16, 1992 (Paper No. 7).
Claims 1-3 and 6 stand finally rejected under 35 U.S.C. § 103
over the teaching of Nishizaka, U.S. 4,981,812, patented
January 1, 1991, in view of the combined teachings of Godejahn,
U.S. 4,506,437, patented March 26, 1985, and O’Mara et al.
(O’Mara), U.S. 5,027,187, patented June 25, 1991, based on an
application filed Nov. 6, 1990. Claim 1 reads:
1. A method of semiconductor integrated circuit
manufacturing comprising the steps of:
forming insulating regions on a substrate;
fabricating gate structures on said substrate between
the insulating regions thereby forming regions between
said gate structure and said insulating regions, said gate
structures having insulating sidewalls, a conducting layer,
and an insulating top layer comprising a first material;
making polysilicon plugs between said gate structure
and said insulating regions;
implanting impurities into said plugs;
oxidizing the surfaces of said plugs and said first
material thereby causing said impurities to diffuse into
the substrate to form source/drain regions of a field
effect transistor, said gate structure being between said
source and said drain regions;
patterning to expose at least selected portions of
the gate structure;
etching to remove both the oxide on top of the first
material and said first material, thereby exposing portions
of said conducting layer but leaving oxide on top of the
polysilicon plugs; and
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