Ex parte LEE et al. - Page 7




          Appeal No. 94-0809                                                           
          Application 07/707,365                                                       
               Fig. 3A does not show a plurality of “insulating regions on             
          a substrate.”  However, Nishizaka teaches at col. 1, l. 18-24:               
                    In a conventional process for providing the                        
               trench separation, field oxidation films are formed                     
               at predetermined regions on a p-semiconductor substrate                 
               by use of a selective oxidation method at a first stage.                
               Although plural field oxidation films are provided on                   
               plural regions of the substrate, a limited section                      
               including only one field oxidation film will be                         
               explained hereinafter.                                                  
               Fig. 3B shows that all the aforementioned films and layers              
          “and an upper portion of the substrate 1 are selectively etched              
          to provide element separating trenches 8" (col. 3, l. 66, to                 
          col. 4, l. 2).                                                               
               Fig. 3C shows that the “inner surface of the element                    
          separating trenches 8 is oxidized to provide trench oxidation                
          films 9" (col. 4, l. 3-5).                                                   
               Fig. 3D shows that “the trench oxidation films 9 are removed            
          on the bottom surface” (col. 4, l. 10-11), “a polycrystalline                
          silicon layer 10 is grown on an overall surface . . . so that the            
          element separating trenches 8 are buried with polycrystalline                
          silicon layer 10" (col. 4, l. 12-16) which “may be doped with                
          impurities to be the same conduction type as that of substrate 1"            
          (col. 4, l. 17-18), and “the polycrystalline silicon layer 10 is             
          etched back on the silicon nitride film 6" (col. 4, l. 18-20).               



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