Appeal No. 94-0809
Application 07/707,365
that this finding is entirely consistent with the examiner’s
finding that Nishizaka “fails to show forming source and drain
regions by implanting dopants into silicon plugs and diffusing
impurities from the doped polysilicon plugs into the substrate”
(Ans., p. 5, first full para.).
Our finding appears also to be consistent with the
conventional processes of making the integrated circuits which
Nishizaka describes in the BACKGROUND OF THE INVENTION, cols. 1-
2. Nishizaka teaches that conventionally (col. 1, l. 31-51;
emphasis added):
. . . a trench oxidation film is formed on the
inner surface of the element separating trenches, and
an oxidation film is then formed on the silicon nitride
film and the trench oxidation films by providing an oxide
having a high re-flow property such as BPSG, etc. After
this, the high re-flow property oxidation film is re-flowed
by a heat treatment of approximately 900 to 1000 C.O O
At the following stage, the re-flowed oxidation
film is etched back to be left in the element separating
trenches, so that the top surface of the film is above
the top surface of the p-semiconductor substrate, and
the silicon nitride film and pad oxidation film are
successively removed. Then, a gate oxidation film is
formed on the p-semiconductor substrate thus processed,
and a polycrystal silicon layer and a WSi layer are
successively grown on the gate oxidation film.
Thereafter, a gate electrode is provided by
defining the polycrystalline silicon layer and the
WSi layer to be a predetermined pattern, and impurities
are then injected to provide a source and a drain of a
transistor . . . .
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