Appeal No. 96-0905
Application No. 08/116,950
clock cycles for each CPU, so that said instruction stream
is executed asynchronously over plural instructions and any
of said CPUs may be leading other of said CPUs, said machine
clock cycles including execution cycles where an instruction
of said instruction stream is executed and stall cycles
where an instruction of said instruction stream is not
executed, each CPU having a memory request input/output
port;
b) a common memory coupled to the input/output ports of
said CPUs, the common memory implementing a memory request
only after receiving identical requests from all of said
CPUs, the memory sending an acknowledge signal to the CPUs
when implementing a memory request, each of the CPUs
executing stall cycles while awaiting implementation of a
memory request by the common memory as signalled [sic,
signaled] by said acknowledge signal;
c) each of the CPUs having a counter to count machine
clock cycles corresponding to execution cycles but which is
inhibited from counting machine clock cycles corresponding
to stall cycles; and
d) said CPUs having an interrupt circuit responsive to
an external interrupt request occurring at any time
unsynchronized with said execution of said instruction
stream, said interrupt circuit being coupled to said
counters in said CPUs and responsive to a selected count in
each of said counters for separately interrupting each CPU
at an identical instruction execution cycle, any one of the
CPUs which may be leading being interrupted first while
other of said CPUs continue to execute instructions so that
if said CPUs are executing different instructions in said
stream then said CPUs may be interrupted at different
instants in real time.
The examiner relies on the following references:
Kreis et al. 3,921,149 Nov. 18, 1975
(Kreis)
Kolb et al. WO 85/02698 Jun. 20, 1985
(Kolb) (PCT)
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