Ex parte LEE et al. - Page 2




          Appeal No. 96-0982                                                          
          Application 08/163,812                                                      


          This is a decision on the appeal under 35 U.S.C. § 134                      
          from the examiner’s rejection of claim 8, which constitutes                 
          the only claim remaining in the application.  An amendment                  
          after final rejection was filed on February 6, 1995 but was                 
          denied entry by the examiner [Paper #6].                                    
          The disclosed invention pertains to an improved                             
          control system for a postage meter.  Specifically, the                      
          invention is directed to the manner in which memory enable                  
          signals are applied to memories having different access times.              
          The single claim on appeal is reproduced as follows:                        
               8.  An improved electronic postage meter control                       
          system having a printing means including means for printing                 
          mixed graphic and alphanumeric information in response to said              
          control circuit, said control circuit including a programmable              
          microprocessor in bus communication with said printing means                
          for controlling said printing means and with a plurality of                 
          memory units for accounting for postage printed by said                     
          printing means, said memory units including at least a first                
          memory unit having a write access time shorter than the write               
          access time of a second one of said memory unit, a program                  
          memory means in bus communication with said programmable                    
          microprocessor having an operating program stored therein,                  
          said programmable microprocessor being able to access said                  
          operating program, an integrated circuit in bus communication               
          with said programmable microprocessor, said program memory,                 
          and said first and second units, wherein said improvement                   
          comprises:                                                                  
               said integrated circuit having an address decoding                     
          module means for generating one of a plurality control signals              
          in a unique combination in response to a respective address                 
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