Appeal No. 96-0982
Application 08/163,812
In the rejection of claim 8, the examiner notes that
Larson discloses application specific integrated circuits
(ASICs) to provide control and timing signals to components of
his system. Since the postage meter of claim 8 was admittedly
old, the examiner asserts that "it would have been inherent to
one of ordinary skill at the time the invention was made that
an ASIC could be used to provide the correct timing and
interfacing signals in any computer system, such as the
claimed postage metering system" [answer, page 2].
Appellants respond that the address decoding module
means, the means for maintaining and the second means for
maintaining as recited in claim 8 are not disclosed in Larson.
Specifically, appellants argue the following:
The ASIC address decoder (28) when it
receives a valid address from the
microprocessor (15) generates the
appropriate chip select and write or
read enable signal enabling access to
the appropriate memory. If the
selected memory is one of the NVMs,
the respective chip select signal is
directed not only to the NVM enable
pin but also to a delay circuit (66 or
66E). The delay circuit delays the
generation of a DTACK signal for a
desired time which is sufficiently
long enough to assure a completed
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