Appeal No. 96-0982
Application 08/163,812
memory access of the NVM unit selected
[brief, page 4].
Thus, appellants argue that there is no disclosure in Larson
of a method whereby the write enable signals are held active
as a result of a delay circuit nor is there anything inherent
which would imply using a wait state system responsive to ASIC
control signals.
The examiner responds again that the claimed operation
is inherent in Larson and that there is no recitation of a
delay circuit in claim 8 [answer, pages 3-4]. Appellants
respond that the examiner’s assumptions to support his
inherency argument are contrary to the conventional practice
in the art [reply brief].
When we consider the rules of claim construction and
the requirements of a reference under 35 U.S.C. § 102, we
agree with appellants that the examiner has failed to
demonstrate that the invention of claim 8 is fully met by the
disclosure of Larson.
Claim 8 is drafted as an apparatus claim in means plus
function form as authorized by the last paragraph of 35 U.S.C.
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