Appeal No. 96-0982
Application 08/163,812
placed on said bus by said programmable microprocessor,
respective ones of said control signals being memory write
enable signals for write enabling said first or second units,
said write enable signals be directed to said respective
memory unit;
means for maintaining said respective write enable
control signals active for at least a first period equal to at
least said write access time of said first memory unit in
response to generation of a respective one of said write
enable control signals by said address decoder; and
second means for further maintaining said respective
write enable control signal active for an additional second
period such that sum period of said first period of time in
combination with said second period of time is at generally
equal to said write access time required by said second memory
unit, said second means be responsive only to said write
enable control signal generated by said address decoder for
write enabling said second memory unit.
The examiner relies on the following reference:
Larson 5,097,437 Mar. 17, 1992
Claim 8 stands rejected under 35 U.S.C. § 102(b) as
being anticipated by the disclosure of Larson.
Rather than repeat the arguments of appellants or the
examiner, we make reference to the briefs and the answer for
the respective details thereof.
OPINION
We have carefully considered the subject matter on
appeal, the rejection advanced by the examiner and the
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