Appeal No. 96-4106
Application No. 08/271,238
McDonald discloses a double redundant processor (Figure
1) that includes first and second master processors 50 and 64.
When the first master processor is in an active state for
processing signals, the second master processor is in a
standby state. Each of the master processors includes first
and second subprocessors 4 and 5 for simultaneously processing
data, control and address signals, and a comparator 6 for
comparing the output signals from the two subprocessors 4 and
5 (column 3, lines 7 through 22).
Appellants argue (Brief, page 8) that:
Claim 26, specifies a “first circuit means,
including second bus means, coupling the first bus
means to the second processor unit for communicating
to the second processor unit data signals from the
first bus means in a manner emulating the memory
means to the second processor uit.” (Claim 26,
lines 11-15). Applicants are unable to find
anything in McDonald et al. suggesting that data is
supplied to one of the CPUs 4, 5 (Fig. 1) or the
subprocessors 26, 29 (Fig. 4) indirectly, i.e., “in
a manner emulating” a memory. To the contrary, Fig.
1 shows the CPUs 4, 5 connected in parallel to the
memory 24 so that both CPUs 4, 5 receive the same
data at the same time. Subprocessors 26, 29 are
similarly corrected [sic, connected] and, this
direct connection of the CPUs 4, 5 used by McDonald
et al. is required, in light of the fact the CPUs 4,
5 are operated in “lock step.” (See McDonald et
al., column 1, lines 63-65.) In addition, claim 26
includes “second circuit means coupled to the first
circuit means to receive and compare address and
5
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