Ex parte TAYLOR et al. - Page 7




                 Appeal No. 96-4106                                                                                                                     
                 Application No. 08/271,238                                                                                                             


                 The act of emulation  can occur in real time as in McDonald,2                                                                                                  
                 or in lag time.  In Figure 4 of McDonald, the second circuit                                                                           
                 means includes the driver 44 and bus 10-4 (coupled to the                                                                              
                 first circuit means via the first subprocessor unit 26),                                                                               
                 address comparator 6-4 which receives the address signals on                                                                           
                 bus 10-4, bus 11-4 which transfers address signals from the                                                                            
                 second subprocessor unit 29 to the address comparator 6-4, bus                                                                         
                 10-1 (coupled to the first circuit means via bus 15-1) to                                                                              
                 transfer data signals from the first subprocessor unit 26 to a                                                                         
                 data comparator 6-1, and a bus 11-1 which transfers data                                                                               
                 signals from the second subprocessor unit 29 to the data                                                                               
                 comparator 6-1.  Any “miscompare” from the comparators 6-1 and                                                                         
                 6-4 will cause error signals to be generated on outputs 51 and                                                                         
                 58, respectively.                                                                                                                      
                          The obviousness rejection of claim 26 is sustained                                                                            
                 because the contested limitations (i.e., the first and second                                                                          





                          2Emulation is defined in the attached excerpts from the                                                                       
                 Encyclopedia of Computer Science, Ralston (Editor), pages 535,                                                                         
                 925, 927 and 928 (New York, Van Nostrand Reinhold Company,                                                                             
                 1976).                                                                                                                                 
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