Appeal No. 96-4106
Application No. 08/271,238
data signals produced by the first processor unit to
address and data signals produced by the second
processor unit to assert an error signal when a
miscompare is detected.” (Claim 26, lines 16-20).
Again, the structure of the “second circuit means”
is not found in the lock-step design taught by
McDonald et al. ‘823.
Nothing in claim 26 requires data to be “indirectly”
supplied to the second processor means, or precludes “direct”
connection of the second processor to the memory.
Figure 4 of McDonald shows a first bus 7 coupling the
memory means 24 to the first subprocessor unit 26 for
communicating address and data signals therebetween, a first
circuit means in the form of a driver/receiver 30, including
second bus 15-1, coupling the first bus 7 to the second
subprocessor unit 29 for communicating to the second
subprocessor unit 29 data signals from the first bus means in
a manner emulating the memory means to the second subprocessor
unit. Appellants’ contentions to the contrary
notwithstanding, the “emulating” or imitation of one system
with another system does not require that the operation of the
imitating system lag the operation of the imitated system.
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