Appeal No. 97-1057
Application 08/160,298
The claimed invention pertains to a data processing
apparatus having an arithmetic logic unit (ALU) with three
separate multibit digital inputs. The ALU performs mixed
arithmetic and Boolean operations on the three inputs. A
shifter is connected to one of the three inputs for shifting
the digital signal received at that input. A mask generator
is also provided which generates a multibit digital mask
signal as one of the three inputs to the ALU. A function
control input to the ALU determines which operations will be
performed on the three multibit digital inputs received by the
ALU.
Representative claim 1 is reproduced as follows:
1. A data processing apparatus comprising:
an arithmetic logic unit having first, second and
third data inputs for multibit digital signals representing
corresponding first, second and third input signals, and a
function control input for receiving a function signal, said
arithmetic logic unit generating at an output a multibit
digital signal representing a mixed arithmetic and Boolean
combination of said first, second and third inputs
corresponding to said function signal, said mixed arithmetic
and Boolean combination including at least the following two
mixed arithmetic and Boolean combinations (1) an arithmetic
combination of only said first and second inputs, and (2) an
arithmetic combination of only said first and third inputs;
a first data source supplying a first multibit digital
signal to said first data input of said arithmetic logic unit;
3
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