Appeal No. 97-1057
Application 08/160,298
a second data source supplying a second multibit
digital signal;
a shifter having a data input connected to said second
data source, a shift control input receiving a shift control
signal, and a data output connected to said second data input
of the arithmetic logic unit, said shifter shifting said
second multibit digital signal an amount corresponding to said
shift control signal and supplying said shifted second
multibit digital signal to said second data input of said
arithmetic logic unit;
a third data source supplying a third multibit digital
signal; and
a mask generator having a data input connected to said
third data source and a data output connected to said third
data input of said arithmetic logic unit, said mask generator
generating a multibit digital mask signal corresponding to
said third multibit digital signal.
The examiner relies on the following references:
Chu et al. (Chu) 4,785,393 Nov. 15, 1988
Pfeiffer et al. (Pfeiffer) 5,146,592 Sep. 08, 1992
Vassiliadis et al. (Vassiliadis) 5,299,319 Mar. 29, 1994
(filed Mar. 29,
1991)
Claims 1-27, 29-68 and 70-97 stand provisionally
rejected under the judicially created doctrine of obviousness-
type double patenting as being unpatentable over claims 1-93
of copending application Serial No. 08/160,111. Claims 1-3,
9-13, 16-27, 34, 36-44, 50-54, 57-68, 75, 77-82 and 95-97 also
stand rejected under 35 U.S.C. § 103 as unpatentable over the
4
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007