Appeal No. 97-4407
Application 08/441,560
selected, while the data is used to program the state of those
nodes selected. The nodes are constructed of various forms of
storage elements including latches, flip-flops and other memory
elements.
On page 6 of the specification, Appellant discloses
that address decoding logic 107 is remotely located near a subset
of internal nodes, subsystem block 2, to be selected. Subsystem
block 2 depicts a subset of internal storage nodes, memory
elements A through P, which can be loaded with program data
applied to data bus 100. During normal system operation, storage
elements A through P operate as simple D flip-flops with a D data
input, a C clock input and a Q output. During a test mode of
operation, storage elements A through P are loaded with the
program data supplied from the serial access register 103 via
global bi-directional data bus 100. Once the serial access
register 103 is loaded with the address and program data, the
control input 102 is then enabled and the address decoder output
111 is activated. Address decoder 107 decodes the address
received on address bus 101. Address decoder output 111 is
applied to load control input LD of storage elements A through P.
3
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Last modified: November 3, 2007