Appeal No. 97-4407
Application 08/441,560
latch has a clock input, a SET and RST for respectively setting
the state of its stored data to all logic "1" or resetting it to
a logic "0" irrespective of the data on the D input terminal.
However, Edwards fails to teach or suggest the storage element
having an additional load input coupled to the selection signal
provided by the address decoder and an additional test data input
coupled to another portion of the plurality of outputs of the
serial shift register as claimed by Appellant.
We have not sustained the rejection of claims 1 through
7 under 35 U.S.C. § 103. Accordingly, the Examiner's decision is
reversed.
REVERSED
KENNETH W. HAIRSTON )
Administrative Patent Judge )
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) BOARD OF PATENT
JERRY SMITH ) APPEALS AND
Administrative Patent Judge ) INTERFERENCES
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