Appeal No. 97-4407
Application 08/441,560
having a clock input, a data input D and an output Q. However,
Appellant's claim 1 further recites that the storage element
comprises "a load input coupled to the selection signal provided
by the address decoder, and a test data input coupled to another
portion of the plurality of outputs of the serial shift register,
wherein the output is alternately forced to another logical state
by the selection signal dependent on the data stream present at
the test data input, and forced to the logical state of the data
input by the system clock."
In reviewing Edwards, we fail to find that Edwards
teaches or suggests this claimed structure, a load input and a
test data input different from the data input. In column 4,
lines 5-16, Edwards teaches that scan latches of a system under
test are divided into groups in which each group may be
addressed. In column 4, lines 27-40, Edwards teaches when a
group is addressed, the addressed group is connected to a group
addressing and initializing circuit. The circuit simultaneously
initializes all the latches of an address group to a predefined
initial state. In column 7, lines 3-13, Edwards teaches the
structure of the scan latch. In particular, Edwards teaches that
each scan latch has a D input terminal for receiving data and a Q
output terminal for outputting the stored data. Also, each scan
7
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