Appeal No. 97-4407
Application 08/441,560
When activated, input LD will then cause the program data applied
to test inputs TI through data bus 100 to be loaded in parallel
into storage elements A through P. Appellant discloses that
this feature advantageously provides increased flexibility in
specifying input test stimulus for each subset of internal nodes
that are selected by the address.
The independent claim 1 is reproduced as follows:
1. An addressable serial test system comprising:
a serial shift register having a clock input, a serial
data input, and a plurality of parallel outputs, wherein a data
stream is clocked into the serial shift register via a shift
clock signal and reflected at the plurality of outputs;
an address decoder having a plurality of inputs con-
nected to a portion of the plurality of outputs of the serial
shift register, and an output for providing a selection signal
dependent on the data stream reflected at the portion of the
plurality of outputs of the serial shift register;
a system clock for generating a system clock signal;
a storage element having a clock input coupled to the
system clock signal, a data input residing at a logical state, an
output, a load input coupled to the selection signal provided by
the address decoder, and a test data input coupled to another
portion of the plurality of outputs of the serial shift register,
wherein the output is alternately forced to another logical state
by the selection signal dependent on the data stream present at
the test data input, and forced to the logical state of the data
input by the system clock.
The Examiner relies on the following reference:
Edwards et al. (Edwards) 5,271,019 Dec. 14, 1993
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