Appeal No. 96-2243
Application 08/327,447
connecting the chip [2] bonding pads to selected contacts on
the printed circuit” as recited in claim 19. Figure 7 shows
that wiring 43 (i.e. second level interconnect) connects to a
terminal (equivalent to 42 in Figure 1A) on the printed
circuit board 4, not chip 2 bonding pads. Even if the
terminal (e.g. 42) were considered as part of wiring 43, it
(the second level interconnect) still does not connect to chip
2 bonding pads,
but rather, through additional elements, to chip 6 (or
possibly chip 1).
In a slight variation of this rejection, the
Examiner’s original rejection designated printed circuit 4 as
the first level interconnect. Here again, we fail to see how
the claim language is met. In particular, where is the second
level interconnect that connects to chip 2 bonding pads on the
one hand, to printed circuit 4 contacts which are located on
the other side (away from chip 2) on the other hand?
We agree with Appellants that the Examiner has not
shown how Kishida reads on the claim 19 language, nor can we
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