Appeal No. 1997-2160
Application No. 07/548,709
chip is a central processing unit (CPU) and a digital signal processing unit (DSP). A static scheduler
partitions execution of the signal processing algorithm between the CPU and the DSP.
Representative independent claim 1 is reproduced as follows:
1. An apparatus, comprising:
in a single integrated circuit chip, the combination of:
a central processing unit (cpu) having a cpu instruction set, an execution unit with an arithmetic
logic unit, a program counter, a bus interface, and an interrupt processor including a non-maskable
interrupt input;
a digital signal processor (dsp) having a dsp instruction set to carry out a digital signal
processing algorithm, an execution unit for carrying out multiply and accumulate operations and an
external interface, said dsp being capable of executing simultaneously with said cpu;
an address bus connected between said cpu and said dsp;
a memory accessible by said cpu and said dsp;
a scheduling means for statically scheduling execution of one algorithm between said cpu and
said dsp, said scheduling means transmitting non-maskable interrupts to said cpu non-maskable interrupt
input to effect execution of portions of said algorithm to be executed by said cpu; and
a data bus connected between said cpu and said dsp.
The examiner relies on the following references:
Ino 4,896,576 Jan. 30, 1990
Tokuume 4,979,102 Dec. 18, 1990
Yamazaki et al. (Yamazaki) 5,293,586 Mar. 8, 1994
(filed Sept. 29, 1989)
2
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