Appeal No. 1997-2160
Application No. 07/548,709
Claims 1 through 9, 22, 23 and 26 through 30 stand rejected under 35 U.S.C. § 103. As
evidence of obviousness, the examiner cites Yamazaki in view of Tokuume with regard to claims 1
through 6, 8, 9, 22, 23 and 26 through 30, adding Ino with regard to claim 7.
Reference is made to the briefs and answers for the respective positions of appellants and the
examiner.
OPINION
We will reverse the rejection of claims 1 through 9, 22, 23, 28 and 30 under 35 U.S.C. §103
but we will sustain the rejection of claims 26, 27 and 29 under 35 U.S.C. § 103.
Turning first to independent claims 1 and 30, each of these claims recites a “scheduling means
for statically scheduling execution” of one algorithm between said cpu and said dsp (claim 1) or "of the
signal processing algorithm between said digital signal processor and said cpu” (claim 30).
Appellants argue that while Yamazaki does disclose a CPU and DSP on a single chip, it differs
from the instant claimed invention because while Yamazaki enables two different routines to be executed
simultaneously by a CPU and a DSP, the present invention enables a single routine to be executed in the
most efficient manner by a CPU and DSP [principal brief-page 5].
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