Appeal No. 1997-4125 Page 2
Application No. 08/261,523
and second amendment after final rejection on May 4, 1997.
Both were entered. We reverse.
BACKGROUND
Manufacturing tolerances, temperature changes, and power
variations have limited the useful length of a parallel
computer bus operating at high data rates. In a computer that
transfers data synchronously with respect to a system clock,
moreover, changing the rate of the clock has required
redesigning the bus.
The invention at issue in this appeal is a self-timed
interface (STI) that transfers data between a host processor
and a peripheral controller. More specifically, the STI
clocks data onto lines of a parallel computer bus while
transmitting the clock signal on another line of the bus.
Upon receipt, the data on each line are individually phase-
aligned with the clock signal, thereby compensating for
manufacturing tolerances, temperature changes, and power
variations. Consequently, the maximum length of the bus is
limited only by its attenuation loss. The bus can operate at
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