Ex Parte PHAM et al - Page 3




          Appeal No. 2003-1365                                                        
          Application No. 09/376,659                                                  

               Representative independent claims 1 and 10 are reproduced              
          bellow:                                                                     
               1. A method for establishing plural core gate transistors              
          on a semiconductor substrate, comprising:                                   
               forming plural core gate stacks on the substrate, each core            
          gate stack having at least one side;                                        
               covering the core gate stacks with a first protective layer;           
               etching away portions of the first layer such that at least            
          intended source regions of the substrate are exposed;                       
               implanting dopant into the intended source regions;                    
               depositing a second protective layer onto the first layer,             
          the second protective layer including high temperature oxide                
          (HTO);                                                                      
               etching the second protective layer such that at least                 
          intended drain portions of the substrate are exposed;                       
               implanting dopant into the intended drain regions to thereby           
          establish plural core transistors; and                                      
               undertaking subsequent manufacturing acts with first and               
          second layers protecting at least the sides of the core gate                
          stacks.                                                                     
               10. A method for making a flash memory device, comprising:             
               forming first and second protective shoulders on core gate             
          stacks, such that dopant can be implanted into a substrate                  
          supporting the stacks to establish transistors and such that                
          charge migration into sides of the gate stacks during interlayer            
          dielectric(ILD) formation and device metallization is prevented,            
          at least the second shoulder including high temperature oxide               
          (HTO).                                                                      




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