Ex Parte Cannata et al - Page 9



              Appeal No. 2006-1049                                                                                       
              Application No. 09/667,826                                                                                 

                     14. These timing signals and electrical biasing signal inputs are illustrated                       
              by lines 22 and 25, respectively, in Figure 1 (col. 6, lines 10-12).                                       
                     15. Focal plane array 10 also receives digital offset correction signals                            
              provided along line 23 which allow individual correction of offsets due to                                 
              nonuniformities in each detector element of the array (col. 6, lines 12-15).                               
                     16. The focal plane sensor controller 14, as its name suggests, provides                            
              intelligent control of the focal plane array 10.  In particular, during initial                            
              calibration of the focal plane array and optional subsequent calibrations, the                             
              uniformity in the individual detector elements in the focal plane array 10 is                              
              detected and digital offset correction coefficients stored in offset coefficient                           
              memory 26 (col. 6, line 66 through col. 7, line 5).                                                        
                     17. Uniformity offset coefficients are thus provided in parallel form along                         
              lines 34 to detector array interface circuit 12, which provides the coefficients along                     
              lines 23 to the focal plane array 10, in synchronism with the appropriate timing                           
              signals to control readout and simultaneous offset correction (col. 7, lines 37-43).                       
                     18. Figures 2 and 3A, 3B and 3C, describe in more detail the readout                                
              circuitry of the focal plane array 10 in accordance with the present invention.                            


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