Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
"replying agent" (iSBC MEM/3XX
memory board) "electrically
coupled together by a system
bus" (Multibus II Parallel
System bus iPSB).
"iSBC MEM/3XX" teaches a
"Controller Subsystem" that
controls access to the "DRAM
subsystem" and the "Cache
Subsystem" and corresponds to a
"memory control apparatus."
Figure 2-1. "[T]he Controller
Subsystem provides the control
logic necessary to perform
transfer cycles on the iPSB and
iLBX buses." Page 2-5.
the requesting agent requesting "Multibus II" teaches that the
access to a memory on the "requesting agent" sends an
replying agent for storing and address and request for access
retrieving data therein over to memory over the system bus.
the system bus, the apparatus See description of transfer
comprising: cycle at sheets 2-44 through
2-49. During the request phase
of the transfer cycle, the
requesting agent puts command
signals on the system bus for
memory access, e.g., SC0*
indicates a request, SC4* and
SC5* indicate a memory access,
and SC6* indicates whether the
operation is a read or a write
(sheet 2-22), and address
signals on the address/data bus
lines AD31* through AD0*
(sheet 2-17). During the reply
phase of the transfer, data is
transferred over the
address/data bus (sheet 2-17).
means, associated with a "Multibus II" teaches that the
replying agent, for detecting a "replying agent," which is
request for initiating an coupled to the system bus,
access to a memory on the detects a command for
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Last modified: November 3, 2007