Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
control signals . . . for performing a page mode type
of memory access" (claim 12).
(2) a "requesting agent requesting access to a memory on the
replying agent for storing and retrieving data therein
over the system bus" (claims 1 and 12). Claim 1 also
recites a "request being made over the system bus by a
requesting agent."
We reject Patent Owner's second argument. "Multibus II"
discloses memory access between a requesting agent and a replying
agent over the Parallel System bus iPSB (e.g., Figure 1-2,
sheet 1-9; Figure 1-2, sheet 2-6). "iSBC MEM/3XX" discloses that
memory access can take place over either the Parallel System bus
iPSB or the Local Extension bus iLBX II (Figure 2-1, page 2-2).
Although Patent Owner argues that memory access would take place
over the iLBX II, which is not a system bus, the references
clearly teach that memory access can take place over the system
bus iPSB.
As to the Patent Owner's first argument, the examiner
responds that modifying "286/100" to provide page mode operation
"would not be beyond the knowledge of one of ordinary skill in
the art, particularly given the numerous patent documents
available at the time of the invention which show the use of a
page mode operation" (EA9), which we interpret to mean that it
would have been obvious to modify the memory controller inherent
in "286/100" to perform page mode operation given the advantage
of page mode operation. The issue is whether it would have been
obvious to modify the cache memory controller on the iSBC MEM/3XX
memory board in "286/100" to utilize the page mode. See, e.g.,
Br37 ("A critical question is whether there is any teaching or
suggestion in the references of record to modify the 286/100
system board by adding a page mode memory controller capable of
accessing the 2164 DRAM in page mode."); Br38 ("The issue is not
whether the cited references teach that it is possible to use a
2164 DRAM in a system they describe, but whether it would have
been obvious to modify such a system to support page mode access
to that DRAM.").
We agree with the examiner that one of ordinary skill in the
art would have been motivated, in general, at the time at the
time of the invention to design a memory controller for page mode
operation to achieve the advantage of a maximum data transfer
rate, i.e. to use a known element for its intended purpose and
advantage.
The weak point in the examiner's rejection is that the
iSBC MEM/3XX board is a "cache-based" memory. Patent owner
argues that a person of ordinary skill in the art would not have
had a reasonable expectation of success of modifying "286/100" to
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