Appeal 2006-1454
Application 09/004,524
Patent 5,483,421
18. A structure to minimize and, in fact, essentially eliminate any thermal
stress due to different coefficients of thermal expansion between the chip carrier
and the circuit board is shown in Figure 4 (col. 6, ll. 32-35).
19. According to the present invention, a conventional integrated circuit
chip 20 is provided which has an array of input/output (I/O) pads 22 on one side
thereof which provides not only input/output signal connections to and from the
chip but also power and ground connections (col. 6, ll. 35-39).
20. A chip carrier 24 is provided which has a top surface 26 and a bottom
surface 28 (col. 6, ll. 44-45).
21. The top surface 26 of the chip carrier 24 has an array of bonding pads
30 which are arranged in a pattern which pattern corresponds to the pattern or foot
print of the I/O pads 22 on the chip 20 (Figure 4; col. 6, ll. 49-52).
22. The bottom surface 28 of the chip carrier 24 has a second set of
bonding pads 32 which are connected to the set of bonding pads 30 by metal plated
vias 34 (col. 6, ll. 52-55).
23. There can be several layers of material forming the chip carrier with
lines 35 formed between each layer and vias 34 interconnecting the various metal
layers (col. 6, ll. 55-58).
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