Appeal No. 95-2861
Application 08/062,237
OPINION
We have carefully considered the entire record before us,
and we will reverse the obviousness rejections of claims 4
through 7.
We agree with the examiner's observation (Answer, page 3)
that Toshikazu "teaches in Figure 2 a non-volatile semiconductor
memory device having floating gate 25, a pair of first lower
control gates 30 and 31 laterally surrounding the floating gate
and an upper control gate 27 formed above." The examiner
acknowledges (Answer, page 3) that "Toshikazu differs from the
present invention in that the upper control gate 27 runs in the
same direction as the pair of first lower control gates 30 and
31."
With this difference in mind, the examiner states (Answer,
pages 3 and 4) that:
Masuoka teaches however in Figures 2-3 that the
upper level control gate 114a may run orthogonal to
lower gates 108a, 108b, and 106. It is noted that
Masuoka teaches 108a, and 108b to be lateral floating
gates surrounding control gate 106. This design is
slightly different than that of Toshikazu which has two
control gates laterally surrounding a floating gate.
It would have been obvious to a skilled artisan to
combine the teaching of Masuoka which shows the upper
gate formed orthogonal to the lower gate layers in
order to achieve integration of the device and conserve
as much wafer space as possible.
Appellant argues (Brief, pages 6 and 7) that:
4
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