Appeal No. 95-1763
Application 08/109,201
2. The application on appeal was filed 19 August 1993.
Appellants claim the benefit of application number 07/590,106,
filed 28 September 1990, now abandoned, pursuant to 35 U.S.C.
§ 120. (Paper 10 at 1.)
3. The invention is a data processing device with a direct
memory access (DMA) circuit for storing data from an input
register into a first memory location and for sending data from
second memory location to an output register. (Paper 1 at 4.)
The DMA has DMA channels 21, each using DMA bus 38 and peripheral
bus 28 to effect transfers among internal memories and between
internal and external memories. (Paper 1 at 14-15.) Specialized
external communications ports 50-55 provide communications with
external devices. (Paper 1 at 14.) Each port has a bi-
directional interface 580 with two eight-word first-in, first-out
(FIFO) buffers 540 & 550. The number of bits in a word
corresponds to the number of conductors in the busses. (Paper 1
at 11-12 & 14.) In split-mode, the buffers operate separately as
an input FIFO buffer 540 and output FIFO buffer 550,
respectively. The reading and writing operations are
independent. (Paper 1 at 62.)
4. The contested limitations are common to all three
independent claims on appeal. In claim 25, the relevant portion
states the limitations as follows:
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